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HFA1135
Data Sheet January 23, 2006 FN3653.6
360MHz, Low Power, Video Operational Amplifier with Output Limiting
The HFA1135 is a high speed, low power current feedback amplifier build with Intersil's proprietary complementary bipolar UHF-1 process. This amplifier features user programmable output limiting, via the VH and VL pins. The HFA1135 is the ideal choice for high speed, low power applications requiring output limiting (e.g. flash A/D drivers), especially those requiring fast overdrive recovery times. The limiting function allows the designer to set the maximum and minimum output levels to protect downstream stages from damage or input saturation. The sub-nanosecond overdrive recovery time ensures a quick return to linear operation following an overdrive condition. Component and composite video systems also benefit from this operational amplifier's performance, as indicated by the gain flatness, and differential gain and phase specifications. The HFA1135 is a low power, high performance upgrade for the CLC501 and CLC502.
Features
* User Programmable Output Voltage Limiting * Fast Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . <1ns * Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . 6.8mA * High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 2M * Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . . 360MHz * Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . . 1200V/s * Gain Flatness (to 50MHz) . . . . . . . . . . . . . . . . . . 0.07dB * Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02% * Differential Phase . . . . . . . . . . . . . . . . . . . . . 0.04 Degrees * Pin Compatible Upgrade to CLC501 and CLC502 * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Flash A/D Drivers * High Resolution Monitors * Professional Video Processing
Ordering Information
PART NUMBER HFA1135IB HFA1135IB96 HFA1135IBZ (See Note) PART MARKING 1135IB 1135IB 1135IBZ TEMP. RANGE (oC) -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 8 Ld SOIC PKG. DWG. # M8.15
* Video Digitizing Boards/Systems * Multimedia Systems * RGB Preamps * Medical Imaging * Hand Held and Miniaturized RF Equipment * Battery Powered Communications
8 Ld SOIC M8.15 Tape and Reel 8 Ld SOIC (Pb-free) M8.15
HFA1135IBZ96 1135IBZ (See Note) HFA11XXEVAL
M8.15 8 Ld SOIC Tape and Reel (Pb-free)
Pinout
HFA1135 (SOIC) TOP VIEW
DIP Evaluation Board for High Speed Op Amps
NC -IN +IN V1 2 3 4
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
8 + 7 6 5
VH V+ OUT VL
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HFA1135
Absolute Maximum Ratings TA = 25oC
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V Output Current (Note 1) . . . . . . . . . . . . . . . . .Short Circuit Protected 30mA Continuous 60mA 50% Duty Cycle ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>600V
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Maximum Junction Temperature (Die Only) . . . . . . . . . . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
VSUPPLY = 5V, AV = +1, RF = 510 (Note 3), RL = 100, Unless Otherwise Specified (NOTE 2) TEST LEVEL TEMP. (oC)
PARAMETER INPUT CHARACTERISTICS Input Offset Voltage
TEST CONDITIONS
MIN
TYP
MAX
UNITS
A A
25 Full Full 25 85 -40 25 85 -40 25 Full Full 25 85 -40 25 85 -40 25 Full Full 25 85 -40 25 85 -40 25 25
47 45 45 50 47 47 0.8 0.5 0.5 -
2 3 1 50 48 48 54 50 50 6 10 5 0.5 0.8 0.8 2 1.3 1.3 0.1 3 60 3 4 4 2 4 4 40 1.6
5 8 10 15 25 60 1 3 3 4 8 200 6 8 8 5 8 8 -
mV mV V/oC dB dB dB dB dB dB A A nA/oC A/V A/V A/V M M M A A nA/oC A/V A/V A/V A/V A/V A/V pF
Average Input Offset Voltage Drift Input Offset Voltage Common-Mode Rejection Ratio VCM = 1.8V VCM = 1.8V VCM = 1.2V Input Offset Voltage Power Supply Rejection Ratio VPS = 1.8V VPS = 1.8V VPS = 1.2V Non-Inverting Input Bias Current
B A A A A A A A A
Non-Inverting Input Bias Current Drift Non-Inverting Input Bias Current Power Supply Sensitivity VPS = 1.8V VPS = 1.8V VPS = 1.2V Non-Inverting Input Resistance VCM = 1.8V VCM = 1.8V VCM = 1.2V Inverting Input Bias Current
B A A A A A A A A
Inverting Input Bias Current Drift Inverting Input Bias Current Common-Mode Sensitivity VCM = 1.8V VCM = 1.8V VCM = 1.2V Inverting Input Bias Current Power Supply Sensitivity VPS = 1.8V VPS = 1.8V VPS = 1.2V Inverting Input Resistance Input Capacitance (Either Input)
B A A A A A A C C
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HFA1135
Electrical Specifications
VSUPPLY = 5V, AV = +1, RF = 510 (Note 3), RL = 100, Unless Otherwise Specified (Continued) (NOTE 2) TEST LEVEL A A f = 100kHz f = 100kHz f = 100kHz B B B TEMP. (oC) 25, 85 -40 25 25 25
PARAMETER Input Voltage Common Mode Range (Implied by VIO CMRR, +RIN, and -IBIAS CMS tests) Input Noise Voltage Density (Note 5) Non-Inverting Input Noise Current Density (Note 5) Inverting Input Noise Current Density (Note 5) TRANSFER CHARACTERISTICS Open Loop Transimpedance Gain (Note 5) AC CHARACTERISTICS -3dB Bandwidth (VOUT = 0.2VP-P, Note 5)
TEST CONDITIONS
MIN 1.8 1.2 -
TYP 2.4 1.7 3.5 2.5 20
MAX -
UNITS V V nV/Hz pA/Hz pA/Hz
AV = -1 AV = +1, RF = 1.5k AV = +2, RF = 250 AV = +2, RF = 330 AV = -1, RF = 330
C
25
-
500
-
k
AV = +2, RF = 250, Unless Otherwise Specified B B B B B B B B B B B B B A RF = 510, Unless Otherwise Specified AV = -1, RL = 100 AV = -1, RL = 50 A A 25 Full 25, 85 -40 25 25 25 25 25 25 3 2.8 50 28 3.4 3 60 42 90 0.07 -50 -45 -50 -45 V V mA mA mA dBc dBc dBc dBc 25 25 25 25 25 25 25 25 25 25 25 25 25 Full 660 360 315 290 90 130 170 0.10 0.02 0.02 0.22 0.07 0.03 1 MHz MHz MHz MHz MHz MHz MHz dB dB dB dB dB dB V/V
Full Power Bandwidth (VOUT = 5VP-P at AV = +2/-1, 4VP-P at AV = +1, Note 5) Gain Flatness (to 25MHz, VOUT = 0.2VP-P, Note 5)
AV = +1, RF = 1.5k AV = +2, RF = 250 AV = -1, RF = 330 AV = +1, RF = 1.5k AV = +2, RF = 250 AV = +2, RF = 330 AV = +1, RF = 1.5k AV = +2, RF = 250 AV = +2, RF = 330
Gain Flatness (to 50MHz, VOUT = 0.2VP-P, Note 5)
Minimum Stable Gain OUTPUT CHARACTERISTICS Output Voltage Swing (Note 5)
Output Current (Note 5)
A A
Output Short Circuit Current Closed Loop Output Resistance (Note 5) Second Harmonic Distortion (AV = +2, RF = 250, VOUT = 2VP-P, Note 5) Third Harmonic Distortion (AV = +2, RF = 250, VOUT = 2VP-P, Note 5) TRANSIENT CHARACTERISTICS Rise and Fall Times (VOUT = 0.5VP-P, Note 5) Overshoot (Note 4) (VOUT = 0 to 0.5V, VIN tRISE = 2.5ns) Overshoot (Note 4) (VOUT = 0.5VP-P, VIN tRISE = 2.5ns) Slew Rate (VOUT = 4VP-P, AV = +1, RF = 1.5k) Slew Rate (VOUT = 5VP-P, AV = +2, RF = 250) DC, AV = +2, RF = 250 10MHz 20MHz 10MHz 20MHz
B B B B B B
AV = +2, RF = 250, Unless Otherwise Specified Rise Time Fall Time +OS -OS +OS -OS +SR -SR (Note 6) +SR -SR (Note 6) B B B B B B B B B B 25 25 25 25 25 25 25 25 25 25 0.81 1.25 3 5 2 10 875 510 1530 850 ns ns % % % % V/s V/s V/s V/s
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HFA1135
Electrical Specifications
VSUPPLY = 5V, AV = +1, RF = 510 (Note 3), RL = 100, Unless Otherwise Specified (Continued) (NOTE 2) TEST LEVEL B B B B B TEMP. (oC) 25 25 25 25 25
PARAMETER Slew Rate (VOUT = 5VP-P, AV = -1, RF = 330) Settling Time (VOUT = +2V to 0V step, Note 5)
TEST CONDITIONS +SR -SR (Note 6) To 0.1% To 0.05% To 0.02%
MIN -
TYP 2300 1200 23 33 45
MAX -
UNITS V/s V/s ns ns ns
VIDEO CHARACTERISTICS Differential Gain (f = 3.58MHz)
AV = +2, RF = 250, Unless Otherwise Specified RL = 150 RL = 75 RL = 150 RL = 75 B B B B 25 25 25 25 0.02 0.03 0.04 0.06 % % Degrees Degrees
Differential Phase (f = 3.58MHz)
OUTPUT LIMITING CHARACTERISTICS Limit Accuracy (Note 5) Overdrive Recovery Time (Note 5) Negative Limit Range Positive Limit Range Limit Input Bias Current
AV = +2, RF = 250, VH = +1V, VL = -1V, Unless Otherwise Specified VIN = 2V, AV = -1, RF = 510 VIN = 1V A B B B A A Full 25 25 25 25 Full 4.5 6.4 -125 25 0.8 -5.0 to +2.5 -2.5 to +5.0 50 80 200 200 5.5 7.3 125 mV ns V V A A
POWER SUPPLY CHARACTERISTICS Power Supply Range Power Supply Current (Note 5) NOTES: 2. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only. 3. The optimum feedback resistor for the HFA1135 at AV = +1 is 1.5k. The Production Tested parameters are tested with RF = 510 because the HFA1135 shares test hardware with the HFA1105 amplifier. 4. Undershoot dominates for output signal swings below GND (e.g., 0.5VP-P), yielding a higher overshoot limit compared to the VOUT = 0V to 0.5V condition. See the "Application Information" section for details. 5. See Typical Performance Curves for more information. 6. Slew rates are asymmetrical if the output swings below GND (e.g., a bipolar signal). Positive unipolar output signals have symmetric positive and negative slew rates comparable to the +SR specification. See the "Application Information" section, and the pulse response graphs for details. C A 25 Full 6.9 V mA
Application Information
Relevant Application Notes
The following Application Notes pertain to the HFA1135: * AN9653-Use and Application of Output Limiting Amplifiers * AN9752-Sync Stripper and Sync Inserter for Composite Video * AN9787-An Intuitive Approach to Understanding Current Feedback Amplifiers * AN9420-Current Feedback Amplifier Theory and Applications * AN9663-Converting from Voltage Feedback to Current Feedback Amplifiers
These publications may be obtained from Intersil's web site at www.intersil.com.
Optimum Feedback Resistor
Although a current feedback amplifier's bandwidth dependency on closed loop gain isn't as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier's unique relationship between bandwidth and RF. All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF, in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier's bandwidth is inversely proportional to RF. The HFA1135 design is optimized for a 250 RF at a gain of +2. Decreasing RF decreases stability, resulting in excessive peaking and overshoot (Note: Capacitive feedback will cause the same
4
HFA1135
problems due to the feedback impedance decrease at higher frequencies). At higher gains the amplifier is more stable, so RF can be decreased in a trade-off of stability for bandwidth. The table below lists recommended RF values, and the expected bandwidth, for various closed loop gains.
TABLE 1. OPTIMUM FEEDBACK RESISTOR GAIN (AV) -1 +1 +2 +5 +10 RF () 330 1.5k 250 330 180 250 BANDWIDTH (MHz) 290 660 360 315 200 90
Care must also be taken to minimize the capacitance to ground at the amplifier's inverting input (-IN), as this capacitance causes gain peaking, pulse overshoot, and if large enough, instability. To reduce this capacitance, the designer should remove the ground plane under traces connected to -IN, and keep connections to -IN as short as possible. An example of a good high frequency layout is the Evaluation Board shown in Figure 2.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly terminated transmission line degrade the amplifier's phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 660MHz (AV = +1). By decreasing RS as CL increases (as illustrated by the curves), the maximum bandwidth is obtained without sacrificing stability. In spite of this, bandwidth still decreases as the load capacitance increases. For example, at AV = +1, RS = 50, CL = 20pF, the overall bandwidth is 170MHz, but the bandwidth drops to 45MHz at AV = +1, RS = 10, CL = 330pF.
Non-inverting Input Source Impedance
For best operation, the DC source impedance seen by the non-inverting input should be 50. This is especially important in inverting gain configurations where the noninverting input would normally be connected directly to GND.
Pulse Undershoot and Asymmetrical Slew Rates
The HFA1135 utilizes a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. In this approach, a composite device replaces the traditional PNP pulldown transistor. The composite device switches modes after crossing 0V, resulting in added distortion for signals swinging below ground, and an increased undershoot on the negative portion of the output waveform (see Figures 9, 13, and 17). This undershoot isn't present for small bipolar signals, or large positive signals. Another artifact of the composite device is asymmetrical slew rates for output signals with a negative voltage component. The slew rate degrades as the output signal crosses through 0V (see Figures 9, 13, and 17), resulting in a slower overall negative slew rate. Positive only signals have symmetrical slew rates as illustrated in the large signal positive pulse response graphs (see Figures 7, 11, and 15).
50 45 40 35 RS () 30 25 20 15 10 5 0 0 40 80 120 160 200 240 280 320 360 400 AV = +2, RF = 250 AV = +1 AV = +1
PC Board Layout
This amplifier's frequency response depends greatly on the care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10F) tantalum in parallel with a small value (0.1F) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. 5
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD CAPACITANCE
HFA1135 Evaluation Board
The performance of the HFA1135 may be evaluated using the HFA11XX evaluation board (part number HFA11XXEVAL). Please contact your local sales office for information. When evaluating this amplifier at a gain of +2, the two 510 gain setting resistors on the evaluation board should be changed to 250. The layout and schematic of the board are shown in Figure 2.
NOTE: The SOIC version may be evaluated in the DIP board by using a SOIC-to-DIP adapter such as Aries Electronics part number 08-350000-10. BOARD SCHEMATIC
510 510 VH 1 50 IN 2 3 4 10F 0.1F -5V GND +IN 8 7 50 6 5 GND QP1 VV+ QN1 QN5 VH 1 +IN OUT V+ VL VGND VV-IN -IN RF (EXTERNAL) VOUT QN3 QP2 QP5 OUT VL QN2 ILIMIT Z +1 200 QN6 QP6 QN4 VH R1 50k V+ 0.1F 10F +5V QP3 QP4
of the amplifier. VH sets the upper output limit, while VL sets the lower limit level. If the amplifier tries to drive the output above VH, or below VL, the clamp circuitry limits the output voltage at VH or VL ( the limit accuracy), respectively. The low input bias currents of the limit pins allow them to be driven by simple resistive divider circuits, or active elements such as amplifiers or DACs.
Limit Circuitry
Figure 3 shows a simplified schematic of the HFA1135 input stage, and the high limit (VH) circuitry. As with all current feedback amplifiers, there is a unity gain buffer (QX1 - QX2) between the positive and negative inputs. This buffer forces -IN to track +IN, and sets up a slewing current of: ISLEW = (V-IN - VOUT)/RF + V-IN/RG
TOP LAYOUT
FIGURE 3. HFA1135 SIMPLIFIED VH LIMIT CIRCUITRY BOTTOM LAYOUT
This current is mirrored onto the high impedance node (Z) by QX3-QX4, where it is converted to a voltage and fed to the output via another unity gain buffer. If no limiting is utilized, the high impedance node may swing within the limits defined by QP4 and QN4. Note that when the output reaches its quiescent value, the current flowing through -IN is reduced to only that small current (-IBIAS) required to keep the output at the final voltage. Tracing the path from VH to Z illustrates the effect of the limit voltage on the high impedance node. VH decreases by 2VBE (QN6 and QP6) to set up the base voltage on QP5 . QP5 begins to conduct whenever the high impedance node reaches a voltage equal to QP5's base voltage + 2VBE (QP5 and QN5). Thus, QP5 limits node Z whenever Z reaches VH . R1 provides a pull-up network to ensure functionality with the limit inputs floating. A similar description applies to the symmetrical low limit circuitry controlled by VL.
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
Limiting Operation
General
The HFA1135 features user programmable output clamps to limit output voltage excursions. Limiting action is obtained by applying voltages to the VH and VL terminals (pins 8 and 5)
6
HFA1135
When the output is limited, the negative input continues to source a slewing current (ILIMIT) in an attempt to force the output to the quiescent voltage defined by the input. QP5 must sink this current while limiting, because the -IN current is always mirrored onto the high impedance node. The limiting current is calculated as: ILIMIT = (V-IN - VOUT LIMITED)/RF + V-IN/RG . As an example, a unity gain circuit with VIN = 2V, and VH = 1V, would have ILIMIT = (2V - 1V)/1.5k + 2V/ = 667A (RG = for unity gain applications). Note that ICC increases by ILIMIT when the output is limited. limiting and the amplifier's normal propagation delay, and it is a strong function of the overdrive level. Figure 36 details the overdrive recovery time for various limit and overdrive levels.
Benefits of Output Limiting
The plots of "Pulse Response Without Limiting" and "Pulse Response With Limiting" (Figures 4 and 5) highlight the advantages of output limiting. Besides the obvious benefit of constraining the output swing to a defined range, limiting the output excursions also keeps the output transistors from saturating, which prevents unwanted saturation artifacts from distorting the output signal. Output limiting also takes advantage of the HFA1135's ultra-fast overdrive recovery time, reducing the recovery time from 2.3ns to 0.3ns, based on the amplifier's normal propagation delay of 1.2ns.
Limit Accuracy
The limited output voltage will not be exactly equal to the voltage applied to VH or VL. Offset errors, mostly due to VBE mismatches, necessitate a limit accuracy parameter which is found in the device specifications. Limit accuracy is a function of the limiting conditions. Referring again to Figure 3, it can be seen that one component of limit accuracy is the VBE mismatch between the QX6 transistors, and the QX5 transistors. If the transistors always ran at the same current level there would be no VBE mismatch, and no contribution to the inaccuracy. The QX6 transistors are biased at a constant current, but as described earlier, the current through QX5 is equivalent to ILIMIT. VBE increases as ILIMIT increases, causing the limited output voltage to increase as well. ILIMIT is a function of the overdrive level ((AV x VIN - VLIMIT) / VLIMIT), so limit accuracy degrades as the overdrive increases. For example, accuracy degrades from +15mV to +70mV when the overdrive increases from 100% to 200% (AV = +2, VH = 500mV, RF = 250). Consideration must also be given to the fact that the limit voltages have an effect on amplifier linearity. The "Linearity Near Limit Voltage" curves, Figures 34 and 35, illustrate the impact of several limit levels on linearity.
AV = +2, RF = 250 2.0 1.5 INPUT VOLTAGE (V) OUT 1.0 0.5 0 -0.5 -1.0 2.0 1.0 0 -1.0 -2.0 4.0 IN 3.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)
TIME (5ns/DIV.)
FIGURE 4. PULSE RESPONSE WITHOUT LIMITING
AV = +2, RF = 250 2.0 IN 1.5 INPUT VOLTAGE (V) 1.0 0.5 0 -0.5 -1.0 OUT 2.0 1.0 0 -1.0
Limit Range
Unlike some competitor devices, both VH and VL have usable ranges that cross 0V. While VH must be more positive than VL , both may be positive or negative, within the range restrictions indicated in the specifications. For example, the HFA1135 could be limited to ECL output levels by setting VH = -0.8V and VL = -1.8V. VH and VL may be connected to the same voltage (GND for instance) but the result won't be a DC output voltage from an AC input signal. A 150mV - 200mV AC signal will still be present at the output.
Recovery from Overdrive
The output voltage remains at the limit level as long as the overdrive condition remains. When the input voltage drops below the overdrive level (VLIMIT/AV) the amplifier returns to linear operation. A time delay, known as the Overdrive Recovery Time, is required for this resumption of linear operation. Overdrive recovery time is defined as the difference between the amplifier's propagation delay exiting
VH = +2.0V, VL = 0V TIME (5ns/DIV.)
FIGURE 5. PULSE RESPONSE WITH LIMITING
7
HFA1135 Typical Performance Curves
VSUPPLY = 5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100, Unless Otherwise Specified
300 AV = +2, RF = 250 250 OUTPUT VOLTAGE (mV) 200 150 100 50 0 -50 -100 TIME (5ns/DIV.) OUTPUT VOLTAGE (V) 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 TIME (5ns/DIV.) 3.0 AV = +2, RF = 250
FIGURE 6. SMALL SIGNAL POSITIVE PULSE RESPONSE
FIGURE 7. LARGE SIGNAL POSITIVE PULSE RESPONSE
200 AV = +2, RF = 250 150 OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.)
2.0 AV = +2, RF = 250 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.)
FIGURE 8. SMALL SIGNAL BIPOLAR PULSE RESPONSE
FIGURE 9. LARGE SIGNAL BIPOLAR PULSE RESPONSE
300 250 200 OUTPUT VOLTAGE (mV) 150 100 50 0 -50 -100 TIME (5ns/DIV.) OUTPUT VOLTAGE (V) AV = +1
3.0 AV = +1 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 TIME (5ns/DIV.)
FIGURE 10. SMALL SIGNAL POSITIVE PULSE RESPONSE
FIGURE 11. LARGE SIGNAL POSITIVE PULSE RESPONSE
8
HFA1135 Typical Performance Curves
VSUPPLY = 5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100, Unless Otherwise Specified (Continued)
200 150 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) OUTPUT VOLTAGE (V) AV = +1
2.0 AV = +1 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0
OUTPUT VOLTAGE (mV)
TIME (5ns/DIV.)
FIGURE 12. SMALL SIGNAL BIPOLAR PULSE RESPONSE
FIGURE 13. LARGE SIGNAL BIPOLAR PULSE RESPONSE
300 AV = -1 250 200 OUTPUT VOLTAGE (V) 150 100 50 0 -50 -100 TIME (5ns/DIV.)
3.0 AV = -1 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 TIME (5ns/DIV.)
OUTPUT VOLTAGE (mV)
FIGURE 14. SMALL SIGNAL POSITIVE PULSE RESPONSE
FIGURE 15. LARGE SIGNAL POSITIVE PULSE RESPONSE
200 AV = -1 150 100 OUTPUT VOLTAGE (mV) 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) OUTPUT VOLTAGE (V)
2.0 AV = -1 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0
TIME (5ns/DIV.)
FIGURE 16. SMALL SIGNAL BIPOLAR PULSE RESPONSE
FIGURE 17. LARGE SIGNAL BIPOLAR PULSE RESPONSE
9
HFA1135 Typical Performance Curves
VSUPPLY = 5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100, Unless Otherwise Specified (Continued)
NORMALIZED GAIN (dB) NORMALIZED GAIN (dB)
3 0 -3 -6
VOUT = 200mVP-P GAIN
AV = +1 NORMALIZED PHASE (DEGREES)
AV = +2 3 R = 250 F 0 GAIN -3 -6 PHASE VOUT = 2.5VP-P
VOUT = 1VP-P
AV = -1 PHASE AV = +2, RF = 250 0 AV = -1 AV = +2, RF = 250 AV = +1 90 180 270 360 1 10 100 1000
0 VOUT = 4VP-P VOUT = 2.5VP-P VOUT = 1VP-P 90 180 270 360 1 10 100 FREQUENCY (MHz) 1000
FREQUENCY (MHz)
FIGURE 18. FREQUENCY RESPONSE
FIGURE 19. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
GAIN (dB)
3 0 -3 -6
AV = +1 GAIN VOUT = 2.5VP-P VOUT = 4VP-P
VOUT = 1VP-P GAIN (dB)
3 0 -3 -6
AV = -1 GAIN VOUT = 1VP-P NORMALIZED PHASE (DEGREES)
VOUT = 2.5VP-P PHASE VOUT = 4VP-P VOUT = 4VP-P VOUT = 2.5VP-P VOUT = 1VP-P 0 90 180 270 360 1 10 100 FREQUENCY (MHz) 1000
0 VOUT = 4VP-P VOUT = 2.5VP-P VOUT = 1VP-P 90 180 270 360 1 10 100 1000
FREQUENCY (MHz)
FIGURE 20. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
PHASE (DEGREES)
PHASE
FIGURE 21. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
1000
NORMALIZED GAIN (dB)
900 BANDWIDTH (MHz) 800 700 600 500 AV = +2, RF = 250 400 AV = -1, VOUT = 5VP-P 300 AV = -1 1 10 100 FREQUENCY (MHz) 1000 200 -75 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC)
3 0 -3 -6 -9 AV = +1, VOUT = 4VP-P AV = +2, RF = 250, VOUT = 5VP-P
FIGURE 22. FULL POWER BANDWIDTH
FIGURE 23. -3dB BANDWIDTH vs TEMPERATURE
10
PHASE (DEGREES)
VOUT = 4VP-P
HFA1135 Typical Performance Curves
VSUPPLY = 5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100, Unless Otherwise Specified (Continued)
0.2 NORMALIZED GAIN (dB) 0.1 0
VOUT = 200mVP-P
AV = +2, RF = 250 AV = +2, RF = 330
630 200 63 GAIN (k) 20 PHASE 2.0 0.63 135 90 45 0 PHASE (DEGREES) NOISE CURRENT (pA/Hz) 6.3 180 GAIN
-0.1 -0.2 -0.3 -0.4 -0.5 -0.6 1 10 FREQUENCY (MHz) 100 AV = +1
0.2
0.001
0.01
0.1
1
10
100
500
FREQUENCY (MHz)
FIGURE 24. GAIN FLATNESS
FIGURE 25. OPEN LOOP TRANSIMPEDANCE
-10 -20 -30 -40 GAIN (dB) -50 -60 -70 -80 -90 -100
AV = +2, 1 OUTPUT RESISTANCE () 1K 100 10 1 0.1 0.01
AV = +2, RF = 250
0.3 1 10 100 FREQUENCY (MHz) 1000
1
10 100 FREQUENCY (MHz)
1000
FIGURE 26. REVERSE ISOLATION
FIGURE 27. OUTPUT RESISTANCE
100 0.1 NOISE VOLTAGE (nV/Hz) SETTLING ERROR (%) INI-
100
0.05 0.025 0 -0.025 -0.05
10 ENI INI+ 1 0.1
10
-0.1
1 1 10 FREQUENCY (kHz) 100
3
13
23
33
43
53
63
73
83
93 103
TIME (ns)
FIGURE 28. SETTLING TIME RESPONSE
FIGURE 29. INPUT NOISE CHARACTERISTICS
11
HFA1135 Typical Performance Curves
VSUPPLY = 5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100, Unless Otherwise Specified (Continued)
-40 -45 -50 20MHz -55 -60 10MHz -65 -70 -5.0 HARMONIC DISTORTION (dBc) AV = +2, RF = 250 HARMONIC DISTORTION (dBc) -45 AV = +2, RF = 250 -50 -55 10MHz -60 -65 -70 -75 -5.0 20MHz
-2.5
0
2.5
5.0
7.5
10.0
12.5
15.0
-2.5
0
2.5
5.0
7.5
10.0
12.5
15.0
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
FIGURE 30. 2nd HARMONIC DISTORTION vs POUT
FIGURE 31. 3rd HARMONIC DISTORTION vs POUT
150 AV = +2 100 LIMIT ACCURACY (mV) 50 0 -50 -100 -150
VH = +500mV, RF = 250
150
VL = -500mV, RF = 250 AV = +2 VL = -1.0V, RF = 250
VH = +500mV, RF = 510 LIMIT ACCURACY (mV) VH = +1.0V, RF = 250 VH = +1.0V, RF = 510
100 V = -1.0V, R = 510 L F 50 0 -50 -100 -150 VL = -500mV, RF = 510 VL = -2.0V, RF = 250 VL = -2.0V, RF = 510
VH = +2.0V, RF = 510
VH = +2.0V, RF = 250 -200 0 100 200 300 400 500 OVERDRIVE (% OF VH) -200 0 100 200 300 400 500 OVERDRIVE (% OF VL)
FIGURE 32. VH LIMIT ACCURACY vs OVERDRIVE
2.0 1.8 1.6 LINEARITY ERROR (%) LINEARITY ERROR (%) VL = -2V 1.4 1.2 VL = -1V 1.0 0.8 0.6 VL = -500mV 0.4 0.2 0 -2.0 -1.5 -1.0 -0.5 0.5 0 AV x VIN (V) 1.0 1.5 2.0 VH = +500mV VH = +1V VH = +2V AV = +2 RF = 250 2.0 1.8 1.6 1.4 1.2
FIGURE 33. VL LIMIT ACCURACY vs OVERDRIVE
AV = +1
VH = +2V
VL = -2V
VH = +1V
VL = -1V 1.0 0.8 0.6 0.4 0.2 0 -2.0 -1.5 -1.0 -0.5 0.5 0 AV x VIN (V) 1.0 1.5 2.0 VL = -500mV VH = +500mV
FIGURE 34. LINEARITY NEAR LIMIT VOLTAGE
FIGURE 35. LINEARITY NEAR LIMIT VOLTAGE
12
HFA1135 Typical Performance Curves
2.5 AV = +2 RF = 250 OVERDRIVE RECOVERY TIME (ns) 2.0 OUTPUT VOLTAGE (V) VH = +2V 1.5 VH = +3V VL = -2V 1.0 VL = -1V VH = +1V
VSUPPLY = 5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100, Unless Otherwise Specified (Continued)
3.6 AV = -1 3.5 +VOUT (RL = 100) 3.4 3.3 3.2 3.1 +VOUT (RL = 50) 3.0 2.9 2.8 2.7 |-VOUT| (RL = 50) |-VOUT| (RL = 100)
VL = -3V 0.5
0 0 100 200 300 400 OVERDRIVE (% OF VH OR VL)
2.6 -50
-25
0
25
50
75
100
125
TEMPERATURE (oC)
FIGURE 36. OVERDRIVE RECOVERY TIME vs OVERDRIVE
FIGURE 37. OUTPUT VOLTAGE vs TEMPERATURE
7.1
1.8 1.7 1.6 VOUT = 500mVP-P FALL TIMES AV = -1
7.0 1.5 SUPPLY CURRENT (mA) RISE/FALL TIMES (ns) 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -75 -50 -25 0 AV = +2, RF = 250
AV = +1
6.9
6.8
RISE TIMES AV = -1 AV = +1 AV = +2, RF = 250 25 50 75 100 125
6.7
4.0
4.5
5.0
5.5
6.0
6.5
7.0
SUPPLY VOLTAGE ( V)
TEMPERATURE (oC)
FIGURE 38. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 39. RISE AND FALL TIMES vs TEMPERATURE
13
HFA1135 Die Characteristics
DIE DIMENSIONS 59 mils x 58.2 mils x 19 mils 1500m x 1480m x 483m METALLIZATION Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kA 0.4kA Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kA 0.8kA SUBSTRATE POTENTIAL (POWERED UP) Floating (Recommend Connection to V-) PASSIVATION Type: Nitride Thickness: 4kA 0.5kA TRANSISTOR COUNT 89 PROCESS Bipolar Dielectric Isolation
Metallization Mask Layout
HFA1135
-IN
VH
V+
OUT +IN
V-
VL
14
HFA1135 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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